//============================================================================
// Name        : controllerModule.cpp
// Author      : fantx
// Version     :
// Copyright   : Your copyright notice
// Description : Hello World in C++, Ansi-style
//============================================================================


#include "global/BxGlobal.h"
#include "fpgaControl/fpga_manage.h"
#include "fpgaControl/onbonsource.h"
#include "fpgaControl/messageDeal/message_deal.h"
using namespace std;


Oint32 main()
{
    //! 初始化配置服务
    // ConfigInit();
    //! 初始化控制模块全局变量
    g_Global = Global::pInstance();
    g_Global->init_global_variable();

    //! 初始化FPGA管理(xser)
    g_OnbonSource = onbonsource::pInstance();
    g_MessageDeal = new message_deal();
    g_FpgaManage = fpga_manage::pInstance();

    while (1)
    {
        sleep(10);
        g_FpgaManage->Brightness_message_dealwith(30);
        g_FpgaManage->SCREEN_fpgactrl_status(SCREEN_LOCK);
        sleep(10);
        g_FpgaManage->Brightness_message_dealwith(150);
        sleep(10);
        g_FpgaManage->Brightness_message_dealwith(255);
        g_FpgaManage->SCREEN_fpgactrl_status(SCREEN_UNLOCK);


/* 
        string dataStr = "data";
        g_FpgaManage->setRunFlag(true);
        g_FpgaManage->updateTimeStamp();

        PhyData_Type phy_data;
        pc_cmd_valid = 1;
        pc_cmd_time = G_timeTicks;

        int len;

        for(len=0; len<dataStr.size(); len++){
            *((Ouint8 *)(&phy_data.dstAddr)+len) = dataStr.at(len);
        }

        if((phy_data.dstAddr< FPGA_DEFAULT_ADDR)&&(phy_data.srcAdd == PC_DEFAULT_ADDR )){

            pthread_mutex_lock(&(fpga_manage::p_fpga_manage->m_fpga_manage));
            fpga_manage::p_fpga_manage->data_from_eth_len = 0;
            fpga_manage::p_fpga_manage->Dealwith1_PC_to_eth(len,(Ouint8 *)(&phy_data.dstAddr));
            pthread_mutex_unlock(&(fpga_manage::p_fpga_manage->m_fpga_manage));

            Oint32 temp = 0;
            do 
            {
                pthread_mutex_lock(&(fpga_manage::p_fpga_manage->m_fpga_manage));
                fpga_manage::p_fpga_manage->reg_IRQ_Dealwith(FPGA_MASTER_VBYONE1,0);
                pthread_mutex_unlock(&(fpga_manage::p_fpga_manage->m_fpga_manage));
                usleep(1);
                temp++;
            }while((fpga_manage::p_fpga_manage->data_from_eth_len == 0) && (temp < 1000*100));

            //返回数据 p_fpga_manage->data_from_eth 长度p_fpga_manage->data_from_eth_len
        }else{

            Ouint32 ret = g_MessageDeal->message_group_deal((Ouint8 *)(&phy_data.dstAddr),len-1, 0);
            g_MessageDeal->swap_phy_head((Ouint8 *)(&phy_data.dstAddr));
            // cal crc
            Ouint8 crc = Utils::BCC((Ouint8 *)(&phy_data.dstAddr), ret + 9 + 1);
            phy_data.data[ret] = crc ;

            
            Ouint32 sendLen = ret + 10 + 1; 
            //返回数据 phy_data.dstAddr 长度sendLen

        } */












    }
    return 0;
}
